Implementation of Delay Reduction and Area Minimization in 128 and 144 Bit Parallel Prefix Adders Using Fpgas

Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs compared to that of conventional Ripple Carry Adder (RCA). However, each type of parallel prefix adder has its own pros and cons and are chosen according to the design requirement of the application. This paper investigates mainly two types of carry-tree adders, the brent kungg adder and the Kogge-Stone adder and compares them. These designs were implemented on a Xilinx Virtex 5 FPGA and found that brent kungg adder occupies less area compared to that of the koggestone adder because of its minimal number of usage of nodes and lesser wiring interconnects . And 128 and 144 bitwdths of the Koggestone adder were also designed and compared to the corresponding bitwidths of the ripplecarry adder and found ripple carry performs faster up to 128 bit and as bitwidths increase beyond 128 bits parallel prefix adders performs faster.